1. Field of the Invention
This invention relates to method and apparatus for simulating the behavior of digital VLSI MOS circuits. In particular, the invention provides a method and apparatus for the accurate and efficient simulation of high performance digital VLSI MOS circuits on the transistor level. Timing and power behavior can be accurately predicted and analyzed using this method and apparatus.
2. Description of Prior Art
Switch-level timing simulation, represented by such programs as MOTIS and RSIM, serves a critical role in the simulation and verification of logic and timing behavior of a digital MOS circuit on the switch level. It is characterized by (1) switched-resistor models instead of complicated analytical models for MOS transistors; (2) event-driven techniques which obviate the need to solve an entire circuit repeatedly; and (3) estimated timing and logic values, in lieu of solving a set of nonlinear ordinary differential equations, to evaluate the impact of an event on a set of nodes and transistors. These characteristics combine to offer a simulation performance and capacity close to that of gate level logic simulators (e.g. 1000 times faster than circuit simulators for circuits with hundreds of thousands of transistors) at an accuracy level typically of 20% to 30% of circuit simulators for typical digital MOS circuits. As more VLSI chips, especially high speed ones, are experiencing electrical problems caused by nonidealities in transistors and interconnections thereof, switch-level timing simulation is becoming an indispensable software tool for the verification of digital MOS VLSI.
Its popularity notwithstanding, switch-level timing simulation, as characterized by the foregoing techniques, suffers from several problems that increasingly limits its accuracy and reliability. The use of event-driven techniques, where an "event" is typically a change in the logic state of a node, is inadequate to deal with sensitive portions of digital circuits in which changes in voltage levels can be critical to the operation of a circuit even though such changes do not necessarily involve change in logic states. A prime example is a sense-amplifier ubiquitous in the design of memory circuits, the purpose of which is to sense and amplify small voltage fluctuations in the output of memory cells.
Further, the event driven technique, as it is used in existing switch-level timing simulators, implies that logic changes are always completed before the next change occurs. This seriously handicaps its ability to deal with feedback and dynamic behavior as well as glitches and other important circuit phenomena.
Another serious flaw in existing switch-level timing simulators is the use of a switched-resistor model for MOS transistors. Though much faster to evaluate than an analytical model, this crude model, coupled with the simplistic estimation method mentioned above, is not capable of dealing with many first-order electrical effects, such as the controlling effect of gate voltage on the source-drain current. As a result, the model yields poor accuracy for circuits which use pass transistors, charge-sharing, dynamic logic, feedback, or need long input rise/fall times. Incorrect logic values and/or grossly inaccurate timing (50% or 100%) can result when this method is applied to some advanced digital circuits.
Finally, an increasing number of digital MOS designs are becoming prone to current and power related problems, in addition to timing problems. Overheated chips and electron migrations in metal lines are but two of the most prominent problems. Existing timing simulation techniques cannot be extended easily to provide current information, leaving the designer of VLSI chips with no software aids to assess current and power behavior of a design.
It can be seen from the above that a more reliable, yet equally efficient, method for VLSI timing and power simulation is desired, especially for the verification of sophisticated and high speed chips. The ability to provide current and power information is also highly desirable to cope with emerging VLSI power design problems.